Proceedings of the European Solid-State Circuits Conference ESSCIRC 2007, S. 476-479, München, September 2007

Spectral PLL Built-In Self-Test for Integrated Cellular Transceivers

Christian Münker¹ und Robert Weigel²

¹ Infineon Technologies AG, 81726 München
²Lehrstuhl für Technische Elektronik, Universität Erlangen-Nürnberg, 91058 Erlangen

Abstract: A built-in self test (BIST) solution for the on-chip spectral verification of a 4 GHz Phase-Locked Loop (PLL) is presented. The PLL is embedded in an integrated cellular RF transceiver in a 130 nm CMOS technology. The BIST blocks enable the detection of catastrophic and many parametric faults by measuring the PLL frequency response and checking for spurious sidebands and excessive in-band phase noise without external test equipment. Multi-tone stimuli with a spurious-free dynamic range (SFDR) of 60 dB are generated on-chip, the PLL RF response is demodulated and digitized in an on-chip digital FM discriminator. Spectral analysis is performed using digital narrowband filtering, achieving an SFDR of 45 dB. The fully digital BIST blocks require a chip area of only 0.06 mm² and do not compromise the performance of the PLL itself.

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