Präsentation auf dem RFIC2004 Workshop "Mixed-Signal Design Methodology & Environment", Fort Worth, USA, Juni 2004.

Fast Simulation of Complex RF Mixed-Signal Systems Using Standard VHDL

Christian Münker

Inhalt: Moore's law also holds true for RF and Mixed-Signal ICs: the implementation of more and more features and complex digital signal processing algorithms makes design and verification of RF ICs a complex task. Analog and digital blocks can no longer be verified independently due to the interaction between domains. An operation often takes several thousand cycles, making transient or even periodic steady state analyses a time consuming if not impossible task. Traditionally, behavioral modelling is used to speed up verification in such cases. However, the use of e.g. Verilog-A or ADS in conjunction with a digital simulator requires complex tool environments and gives only a moderate improvement in simulation speed. The little known analog behavioral modelling capabilities of plain VHDL offer a fast and effective way to co-simulate DSP, control and sequencing blocks with analog blocks like ADCs, filters or PGCs.

This presentation introduces RF and analog designers to the possibilities of pseudo-analog modelling using VHDL. It shows in detail how analog blocks like VCO and loop filter can be modelled in an efficient way. PLL analog behavior is simulated using these models, showing settling of the loop filter voltage and spurious sidebands of the VCO signal. Another main topic will be noise which is included in the models as timing jitter and amplitude noise. A quick review of the relationship between phase noise and timing jitter will be given first.

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Eine Präsentation zu diesem Thema in deutscher Sprache finden Sie hier.