My Job Life

The young scientist ...

In 1993 I passed my final tests for the "Diplomingenieur der Elektrotechnik" (Dipl. Ing.) at the RWTH Aachen in Germany. This is equivalent to a Master Degree (M. Eng.) in Electronic Engineering (Solid State Devices). My first employer was a small ASIC design house in Chemnitz, Germany, where I worked on some mixed-signal chips. After three years I moved to the Munich design center of Plessey Semiconductors to work on mixed-signal cell libraries. The design center was closed down one year later in 1997 after Plessey was acquired by Mitel and since then I work for Siemens Semiconductors which became Infineon Technologies in April 2000.

During that time I have worked on various projects as an analog- or mixed-signal design engineer, some of which were:

CMOS analog building blocks of a microcontroller for consumer applications (my training on the job)
a mixed-signal BiCMOS chip to read-out capacitive inclination sensors.
a cell library of robust crystal oscillators for various technologies
frequency synthesizers for several highly integrated transceiver chips for GSM mobile phones in BiCMOS- and CMOS technologies. In these projects, I was also responsible for mixed-signal verification strategies and substrat cross-coupling problems.

Frequency synthesizers or Phase Locked Loops (PLLs) are a long-time favorite of mine: They are being used for frequency synthesis (think of the digital display in AM- and FM-radios or the multi-GHz clock in modern computers) and synchronisation - a "running" picture in TV shows a failed synchronization between the TV station and the receiver at home. It is no exaggeration to say that nearly every modern electronic device contains at least one PLL. Nevertheless, PLLs are still a complex and tough topic which keeps engineers and scientists busy for more than 70 years now. Here, control and communication theory meet with high frequency circuitry - the different time constants and frequencies within a PLL make simulation and measurement a challenging task. On top of that, growing requirements of wire-bound and wireless communication ask for ever faster and lower-noise PLLs. And the mixing of fast digital signals and sensitive analog circuit blocks on one chip creates unexpected cross-coupling.

In some of the projects I was reponsible for the whole project, in others for parts of it. My main job was and still is the design of analog and digital integrated circuits. However, due to the weak economy time- and cost-pressure have grown tremendously in the last years and put a strong focus on testing and verification methods: A full production run for a chip takes several months, the costs for the masks alone in modern technologies are well above half a million €. A bug in the design that is only found on the chip thus can easily make a project unprofitable, delays may lead to missing the market window.

For that reason, I started dealing with improvements of design flow and testability, i.e. I 'm trying to avoid bugs or find them early during the design phase. One way to achieve this is to apply proper simulation and verification strategies, another to include building blocks on the chip for testing and calibration which also speed up the debugging phase and the production test. This was also the topic of PhD thesis which I finished in 2010.

In 2007 I "changed sides" and became a professor at the Munich University for Applied Sciences, teaching analog electronics and digital signal processing. At Infineon Technologies I discovered that teaching can be fun and so moving to a university was a natural step for me. At our lab I can still do mixed-signal circuit design, making it the ideal job for me.

Publications and further informations about my job life can be found under [Publications] and the following links: